1. Field of the Invention
The present invention relates to the field of digital electronic circuits, specifically, VLSI circuit design and operation. In one aspect, the present invention relates to a technique for flexibly controlling circuit performance by providing a programmable delay between circuit elements.
2. Description of the Related Art
Generally, VLSI circuit design entails coordinating the connection and interaction of multiple complex circuit elements such that the overall circuit performance is achieved by the propagation of signals throughout the overall circuit. Given the complexity of such circuits and the varying conditions and propagation path lengths for circuit signals, it can be difficult to design the circuit so that an appropriate delay is provided to maintain the necessary timing interval between two events. This is often called “self-timed-margin.” This difficulty arises for a variety of reasons. For example, a specific delay may not scale proportionally over process variation, voltage variation or temperature variation. As a result, delay that is appropriate at one simulation condition can be insufficient at another condition. For example, a delay design which is appropriate at nominal condition often violates the timing margin constraints at burn-in condition (which imposes very high voltage and temperature). To meet the timing margin constraint across all the conditions, conventional approaches can result in circuit over-design to keep more-than-needed margin at nominal operation conditions, which results in performance loss.
FIG. 1 shows a conventional delay generation scheme used in the context of a memory circuit 10 having an address predecode circuit 14, address decoder circuit 16 and a memory array 18. As depicted, address data 11 for selecting a particular memory cell from the memory circuit 10 are input to the address predecoder circuit 14 which includes a plurality of logic gates for generating a predecode signal 15 (“predec”) that is provided to the address decoder circuit 16. Based upon the predecode signal 15, address decoder 16 selects a particular wordline (e.g., wordline 19) using address decode logic contained within the address decode circuit 16. As the wordline signal 19 propagates through the memory array 18 to select a row of memory cells, including memory cell 20, bitline selection logic (not shown) also generates bitline selection signals to connect the memory cell 20 through bitlines 21, 22 to the sense amplifier 23 for generating a data output 25 (“dout”) from the memory.
Persons skilled in the art will appreciate that the particular address decode logic comprises a plurality of logic gates (e.g., gates 17) that will impose a predetermined amount of delay on the propagation of the wordline selection signal. To allow sufficient time for a differential signal to be developed across bitlines 21 and 22 before the sense amplifier 23 is enabled, an enable signal 24 for the sense amplifier is generated from the predecode signal 15 output from the predecode circuit 14 using a fixed delay circuit 26 coupled between the address predecode circuit 14 and the sense amplifier 23. As shown, the fixed delay circuit comprises an OR gate coupled to inverters which serve to generate a single delayed version of the precode signal 15. The sense amplifier enable signal 24 must be slower than the wordline select signal 19 to allow sufficient time for the data stored in the memory cell 20 to propagate as a differential signal across the bitlines 21, 22 so that the sense amplifier 23 can operate properly.
The operation of the conventional approach is shown in FIG. 2 which depicts a timing diagram for selected signals generated in the memory circuit example of FIG. 1. As shown in FIG. 2, a clock input 8 to the memory circuit 10 is received at the address predecode circuit 14 which acts upon the input address data 11 to generate a predecode signal 15 as an output from the address predecode circuit 14. As shown, the rising edge of the predecode signal 15 propagates through the address decoder 16 to generate a transition in the wordline 19 that is used to select memory cell 20 from the memory array 18. In addition, the predecode signal 15 also propagates through the fixed delay circuit 26 to cause a transition in the sense amplifier enable signal 24 which occurs at a predetermined interval 29 (tmargin) after the wordline signal transition. As will be appreciated, the delay in the transition of the sense amplifier signal 24 must be sufficient to permit wordline and bitline selection signal propagation, but must also permit sufficient time for a differential signal 27 to develop across the bitlines 21, 22 which must overcome circuit capacitance (for example, from the bitlines, memory cells, sense amplifier, etc.) and imbalances of the capacitance. This is shown in FIG. 2 as the minimum time interval “tbitline” 28.
While it is known that a predetermined delay must be provided between circuit elements so that the sense amplifier is enabled after the memory cell is connected to the bitlines, the use of a fixed delay circuit 26 does not provide for flexibility in selecting among multiple delay intervals depending upon circuit operation requirements or other considerations. In addition, even within a particular circuit application, the use of the same fixed delay circuit 26 in multiple portions of the same circuit may result in undesirable signal delays where the desired delay does not scale proportionally over the entire circuit, due to process variations, voltage variations, temperature variations, or other inconsistencies in the circuit design or construction.
Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.